Curtiss-Wright’s HPEC radar architecture meets USAF-led NGR processor study
Curtiss-Wright's Defense Solutions division has announced that its high-performance embedded computing (HPEC) radar processing architecture met the US Air Force (USAF)-led Next Generation Radar (NGR) Processor Study's target benchmarks.
The study is aimed at assessing the capability of cost-effective commercial-off-the-shelf (COTS) hardware and software to perform airborne radar signal processing,
It involved the company optimising Synthetic Aperture Radar (SAR) and Ground Moving Target Indicator (GMTI) benchmarks on a solution comprised of its recently introduced OpenHPEC Accelerator Suite development tools, five OpenVPX DSP modules and a 40 Gbps OpenVPX Ethernet switch module.
The study involved the company testing the current generation as well as upcoming next generation OpenVPX modules.
Curtiss-Wright Defense Solutions division senior vice-president and general manager Lynn Bamford said: "We are very pleased to be able to announce that our HPEC Radar system architecture, along with our OpenHPEC suite of development tools, provides the performance and survivability needed to meet the USAF's demanding radar processing requirements with cost effective COTS technology.
"We have successfully demonstrated how our cost-effective open architecture DSP and network switch building blocks, along with our industry-leading open standard-based OpenHPEC Accelerator Suite of software tools can be effectively used to design whole new classes of rugged deployed HPEC solutions that deliver all of the proven cost savings and long lifecycle benefits of COTS technology while elevating radar processing performance to levels never before achievable."